First time soldering my own chip! 👏
It's also the first time I've used a stencil.
The chip is my Greyhound v1 (http://github.com/mole99/greyhound-ihp), designed for the IHP SG13 process family.
Read on for the full thread ⬇️
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mole99
@mole99@fosstodon.org
mastodon 4.7.3Hi! I'm Leo, an open-source silicon advocate. This means that I'd like to advance chip design using open-source EDA tools and open-source PDKs. I am one of the maintainers of LibreLane and I regularly contribute to the three open-source PDKs (sky130, gf180mcu and ihp-sg13).
So how did I get there? Well, I wanted to understand computers at the deepest level, and transistors are pretty much the bottom of it all as far as I'm concerned :)
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Joined March 30, 2019
Leos Blog:
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The shuttle includes various RISC-V SoCs, a "3D" ray caster, a 100Mbps 4-port Ethernet switch and beacon, a dual Core BIO from #Baochip1x, three different #TinyTapeout chips, and much more!
There are also a number of designs that use the new community-created standard cell library, which is both faster and uses less power: a Linux-capable RISC-V SoC with MMU and FABulous FPGA.
Finally, there are new SRAM macros and inductors for validation and characterization, to be used in future runs.
A Tiny FABulous FPGA on Tiny Tapeout? It's more likely than you think!
Yesterday the TTIHP26a shuttle (https://app.tinytapeout.com/shuttles/ttihp26a) from #TinyTapeout has closed. In it, hundreds of incredible projects.
You can view the full shuttle and its designs here: https://app.tinytapeout.com/projects/3744
I had the opportunity to submit an FPGA, which I created using my FABulous LibreLane plugin. For this fabric, I developed a "tiny" tile library that better fits the constraints of Tiny Tapeout.
Greyhound is alive! 🐶
Last week, I posted about soldering my custom chips onto breakout boards. Now, I can finally say that Greyhound is working 🎉
If the video below doesn't work, you can also view it on Peertube: https://makertube.net/w/3rQ8a7WxTYcr1BQY9nCUat
I'm incredibly happy that Greyhound is no longer just theoretical, but that it can run examples on its FPGA in the real world 🤩
Greyhound repository: https://github.com/mole99/greyhound-ihp
And another chip submitted for tapeout - HeiChips 🎉
This one has been in the works for some time, but since the shuttle was canceled last fall, it was postponed to a later one.
It's an open-source chip featuring user projects created by participants of the HeiChips Summer School 2025 (https://heichips.github.io/). How cool is that?
The chip uses 9mm² of silicon on SG13CMOS and has been submitted to IHP's Low-Cost MPW shuttle (https://dk.ihp-microelectronics.com/OpenSourceRequest.php).
More below ⬇️
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If you would also like to tape out, registration for the second shuttle run is currently open: https://buy.wafer.space/
LibreLane 3.0 has officially been released! 🎉
With this release, LibreLane finally has a logo! What's more, we now have a website showcasing LibreLane's capabilities, as well as a blog featuring development updates and announcements.
Read the full blog post here: http://www.librelane.org/blog/2026-03-25-website_release_3-0
LibreLane website: https://librelane.org/
Install LibreLane today: http://docs.librelane.org/
Tiny Tapeout is hosting the first demoscene competition for ASICs! 🕹️
Get ready to compete with your own design and win a variety of prices, including whole wafers! Or you just do it for fun 😉️
The goal is to create a design that targets 2 tiles or less and uses the Tiny VGA Pmod to create nice visuals and the Audio Pmod to play some cool tunes!
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The chip was implemented using the wafer.space LibreLane template (https://github.com/wafer-space/gf180mcu-project-template) and uses Yosys and nextpnr for the FPGA toolchain.
You can find all projects from the first wafer.space run here (ID: G801MOLE): https://github.com/wafer-space/ws-run1
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@WillFlux@mastodon.social Thanks! Yeah, there's a good reason for that: getting the hardware right is one challenge, but having software support for your FPGA is another challenge entirely. FABulous and Yosys/nextpnr solve the second problem with ease.
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@tyalie@chaos.social @mithro@fosstodon.org @matthewvenn@chaos.social You should also familiarize yourself with simulating your design using simulators such as Icarus Verilog or Verilator via cocotb, for example.
The fundamental knowledge you gain from FPGA design can easily be transferred to ASIC design.
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@tyalie@chaos.social @mithro@fosstodon.org @matthewvenn@chaos.social Yes, Tiny Tapeout is ideal if you want to start with ASIC design right away.
As for my personal journey, I started out using the open-source FPGA toolchain (Yosys and nextpnr) with various open-source FPGA boards, such as the excellent iCEBreaker and ULX3S.
I'd recommend learning (System)Verilog or another higher-level HDL that compiles down to it, since Verilog is usually well supported by the open-source tools.
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@gregdavill@chaos.social I'm gonna have to say, you're not the only one. I need to finish my board too 😶
But I've been busy with preparations for run 2 😄
Good luck with the blinky! 🤞