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aki-nyan
@lethalbit@chaos.social
mastodon 4.6.9abyssal witch | deranged catgirl hardware/software engineer + vtuber | that crazy SCSI girl | she/her
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Joined April 18, 2022
Pronouns:
she/her
Codeberg:
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VTuber:
being trans is one of the most punk things you can do, heck ya
what if: catgirl, but *big*
Did you know there are terminal control codes for progress reporting?
Did you know that KDE's Konsole partially implements them?
is there anynyan out there that actually likes the taste of cucumber? especially raw? I just can't wrap my head around it.
Boosted by @joe@f.duriansoftware.com
TIL that COBOL finally got the XOR operator in, uh, checks notes 2023
did you know: meow
Replying to
@NullTheFool@mastodon.gamedev.place As far as I know, there is no performance improvement, as they are basically discarded by the interpreter
I think catgirls should get a weekly stipend for energy drinks and FPGAs...
I think more FPGA dev boards should break out a diff-pair into just some SMA connectors on the board, not even from the SERDES (those too) but just, like, some global clock capable/LVDS IO,
It would be super useful I think.
Semi-related, any of my EE friends have a good source for some high-quality, but not too expensive 50Ω SMA to BNC adapters and SMA cables?
Question for FPGA/ASIC friends, anynyan know of a good huge collection of RTL files?
I need to build a massive corpus for profiling a language frontend, I'm thinking about seeing what I can slurp from OpenCores, but if there are pre-built corpora out there I am interested.
I'm also working on putting together an HDL standard verification suite for Verilog/SystemVerilog/Verilog-AMS/VHDL/VHDL-AMS, so eventually forming corpora for all of those would be nice.
Replying to
@NullTheFool@mastodon.gamedev.place As for if people use them at lot, Not quite, but I use them for everything where I can, it helps ensuring your code is correct, so people *should* use them more imo
I don't care what anynyan says, Itanium was a cute ISA
software-defined-catgirl
I do hope, that one day (very soon, hopefully) my yearn for squish will overcome my stupid anxiety and mental block with trying to learn to draw,
Especially as that way I can do that for hours rather than spend 8h fighting symlinks...
I am sleepy, I require squishy naps
Oh oh oh, also also, happy lesbinyan visibility week~
Say, people migrating from GitHub to Codeberg/Forgjo,
How are you all handling things like the PyPi trusted publishing, pages, and cross-architecture builds?
the polygons are stored in the tits
Going to submit a patch to pytest that plays the Wilhelm scream every time a run fails
just had another terrible idea, I wonder how painful this will be to execute.
it sure is cool how my brain has the amazing ability to *instantly* make me feel awful out of literally nowhere regardless of what or how things were going.
Also the fact my ADHD meds don't work as well unless I am /also/ taking 600mg of caffeine a day is kinda bullshit if you ask me
Boosted by @kkarhan@jorts.horse
Replying to
Well, did it anyway, I guess, https://github.com/bytecodealliance/wasmtime/pull/13157
"Aki just go get more" I hear you say, but alas, I can not, I have a grand total of 2.36USD in my account right now and have yet to manage to focus to put in enough work so I can submit an invoice, bweeeeeeeh,
It'll be fine, I'm just wiggly and whiny, don't mind me,
Say, rust friends, anyone know of a good library to do mesh triangulation/tetrahedralization and refinement?
The inputs would be primarily 2D outlines, sometimes with holes, all fully manifold, and potentially non-sparse N*M matrices representing present/non-present points on a plane. Ideally supporting mesh refinement and tuning
Is the best option to just link with gmsh and figure things out from there?
I also need to figure out VTK/HDF5 seralization too, bweh.
Replying to
@cmb@cathode.church AH I TOTALLY MISSED THIS I'M SORRY T~T
If it's not too late I can give it a look later today
Unrelated, anyone who uses podman/docker, any suggestion on how to deal with huge install packages when building an image?
I don't have to have to copy a 150GiB file into the context, to then install and then delete, is there a way to like, only temporarily mount the host FS when building?
I lost two of the little rubber feet (I swear they were called lerfs? lurfs? at one point but I can't ever find that again) for my Versa board so now it's all tippy, and I don't have a bracket for it in my paws yet, RIP.
Oh well.
Gotta try to buckle down and fix SRAM programming today
Surprised this got approved and merged without any pushback,
I expected at least some due to changing default behaviour out from under users, but *shrug*
ugh, I am out of caffeine and I have the worst caffeine withdrawal headache, and I can't get more until next month, bweh
Replying to
@North Yee!
If you go about it and stay in Python land, you can likely just yoink a large chunk of the stuff I've written there with some adaptation (yay BSD-3-Clause :v)
Having a full PCAPNG serializer in Python is not super ideal, but hey it works.
I've actually thought about making a proper extcap library thingie for Python eventually, but i've not had the need quite yet as i've only had to do this twice :v
(which is not a lot but still more than a one-off at this point, lol)
Replying to
@North Have you thought about also possibly setting some wireshark extcap stuff for them too?
I recently did that for USB stuff https://github.com/shrine-maiden-heavy-industries/sol/pull/13
But yeah these look awesome!
Also, ugh, need to figure out why my SRAM programming routine is broken,
It keeps resetting the FPGA which then dumps the SRAM we /just/ programmed and it boots from FLASH again, lmao...
for as CISC-Y as AMD64 is, it still doesn't have just a "reverse the bits in this register" instruction, huh?
Replying to
@artemist Yeah, only in Zbkb though, which I don't think has landed in any real silicon yet, :v
Replying to
granted it's a *1* instruction saving here, but *shrug*
for as CISC-Y as AMD64 is, it still doesn't have just a "reverse the bits in this register" instruction, huh?
Replying to
(I may or may not be constantly thinking about https://bsky.app/profile/catboymech.art/post/3lsicfvppx22y on and off every other day *cough*)
The stackup looks kinda silly without any blind/buried Vias, lmao
I am in need for a latched comparator with a 15ps rise/fall time....
Ya know, just a casual 66GHz ....
Annie, what are you doing?
Ugh, I need to bitch at Xilinx about the IBIS-AMI models *AGAIN*
I should also ask them about how they expect licensing to work for CI runs.
This would be so much easier if I had a proper technical contact at AMD/Xilinx, but they refuse to do so.
It's annoying, just because i'm not buying 6-digits worth of hardware/software from them it's as if I don't exist.
Which I get, but still, at least a *little* consideration for us FOSS/OSHW players would be nice, ya know?