Craig Bishop

@tom_verbeure@mastodon.social FYI @azonenberg@ioc.exchange the ngscopeclient DP AUX decoder is way better than Saleae’s Manchester decoder (+ my minimal HLA) 👍. If I really need to dive deep, I’ll probably export a VCD so I can use ngscopeclient’s decoder

@tom_verbeure@mastodon.social these are on a Saleae MSO with their software and a custom HLA (partial) for the DP AUX protocol. I was using ngscopeclient too, but the 20 channels of logic analyzer inputs are so handy for general troubleshooting on an FPGA. I’ll have both together soon as I bring up the main link. I just doubled the timeout to 600 us for now. No sense being a stickler about the spec I guess. Compatibility testing for commercial DP sources must be _fun_.

Late last night, I found out one of the issues with my DisplayPort source. It turns out that the 300 µs timeout in the spec is a bit of a... guideline. The display I'm connected to responded in 307 µs for native writes. My AUX link layer was retrying repeatedly after 300 µs timeouts, and then failing after 7 retries. The real discovery was that if your firmware writes 0 to the timeout control register, then your AUX link will just retry immediately! Such unexpected behavior 😝

I should always just search aliexpress before I start designing a board. $8 and shipped next week. Now I skip to working on my SpinalHDL DisplayPort IP.

All hail his scopeness 🙇‍♂️

Ummm… I think I made a knob with too _little_ friction. This is at least an easier starting point than too much friction. I really don’t feel like mucking around with the greases and gels that professional encoders use though. Hmmm.

I appreciate a socketed fuse

Marvell 88E1512 Ethernet PHY

These piano key style DIP switches are kind of fun. I’ve never has those before. They’re harder to actuate than I expected…

@0h00000000@ioc.exchange Are you doing just video, or data islands for audio too? I found that some monitors don't like the guard band symbols when there's no packets in the blanking period. DVI doesn't have those, so I guess it makes sense.

@0h00000000@ioc.exchange My DVI code, SpinalHDL though so probably less useful. I can output verilog for the HDMI IP standalone if interested—I haven’t spent the time to make it easy or document standalone usage yet. It’s also tied to Xilinx DDR primitives only right now. Maybe useful for reference though https://github.com/craigjb/spiny/tree/main/spinal/spiny/hdmi https://github.com/craigjb/spiny/blob/main/examples/hdmitest/spinal/HdmiTest.scala

@0h00000000@ioc.exchange Do you have a good project storage solution already? My closet is let’s say… on its way to being organized 😝

@azonenberg@ioc.exchange timing couldn’t be better! I’ve just about implemented an aux channel PHY and transaction layer that needs testing with a real monitor now. Btw, don’t mention this CDMA stuff to VESA people or the next spec may require Qualcomm patent licenses 😝

@azonenberg@ioc.exchange I’m planning to move future designs to USB-C and DP alt mode. HDMI is useful for RPi, but DP is so much more convenient with FPGA transceivers!

@azonenberg@ioc.exchange I landed on a design with a separate descriptor file so I don’t have to put the data in ROM. Then a BSCANE2 exposes the capture RAMs over JTAG. Not configurable triggers or comparators yet….

I know they’re tight spots, but the test point labeling is a bit messy and unclear

@infosecdj so much CMP fill!

@0h00000000@ioc.exchange if the PCIe hard IP has low level PMA access, then _maybe_. Not sure I’d sign up to do that on a client project though. Who needs a display anyway, video on SSD is better. Just need to put the marketing spin on it! If you have hard MIPI ports, that TI solution sounds pretty drop-in, no? Does it handle the aux channel software stack too? That’s the *fun* I’m staring into now.

@0h00000000@ioc.exchange DDR IOs could probably handle the 720p display? With RB modes, it’s only in the range of 600-ish Mbit per color channel I thought. Do you need 60 Hz? 720p30Hz 🤔

@0h00000000@ioc.exchange do you use the internal dividers in practice?

@0h00000000@ioc.exchange Ok, you may have convinced me those pricy bins are worth it. Stackable, divideable, optional lids, wide sizes with vertical walls (the sloped walls on sterilite bins really annoy me for this use case)

@0h00000000@ioc.exchange Or your wire is too small

@0h00000000@ioc.exchange do these super LEDs go with the FPGA video system in the same project?

@azonenberg@ioc.exchange The recent licensing changes also got me thinking about revisiting my SpinalHDL ILA design too. Are you thinking of an ILA interface to ngscopeclient that could support other ILAs too? Like if my ILA exposes a certain register IF or ROM blob descriptor?

@azonenberg@ioc.exchange I should grab an Efinix board too—definitely not a fan of a Versal-ified future. I’m still kinda put off by hard blocks that are only GUI configurable though..

@azonenberg@ioc.exchange Ah, so CDMA is how DP handles multi-stream with multiple displays on the aux channel 😝

@azonenberg@ioc.exchange Which IAQ monitors?

@azonenberg@ioc.exchange that’s one of my favorite features so far. Also it makes scrolling through the decodes easier since I can see the boundaries at a glance.

@whitequark@social.treehouse.systems @azonenberg@ioc.exchange I saw this “related product” on the page. It seems… perfectly safe? /s The woman in the video isn’t even wearing goggles. https://www.tbklasermachine.com/tbk-2206-laser-soldering-machine-with-integrated-thermal-camera.html